RISC-V International

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Comment: updated spec status, added N/A to Compiler/toolchain sections

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  • Test plan for the fast-interrupt is available.
  • YAML config needs to be created. See here.

Compilers / Toolchains

TBD

GCC and Binutils

  • TBDN/A? No new instructions are added

LLVM

  • TBDN/A? No new instructions are added.

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

  • TBD - Waiver until SAIL privilege model is completed?

Spike

  • TBD

riscvOVPSimPlus

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Project/MaintainerDescription






ABI Extensions (no new ABI required)

  • Regular C function that save/restores all caller-save registers
  • Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
  • EABI Task Group - improve interrupt latency by reducing the number of caller-save registers