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• Latest Draft Fast Interrupt Specification (v0.9-draft-20210406)20210422)
  • updated adoc format to align with risc-v template, added revision history
• What's next:
  • 35 outstanding issues to be addressed.

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• Test plan for the fast-interrupt is available.
• YAML config needs to be created. See here.

Compilers / Toolchains

TBD

GCC and Binutils

• TBDN/A? No new instructions are added

LLVM

• TBDN/A? No new instructions are added.

Simulators

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

• TBD - Waiver until SAIL privilege model is completed?

Spike

• TBD

riscvOVPSimPlus

• Imperas Commercial Simulator
• Freeware version
• Support for:

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ABI Extensions (no new ABI required)

• Regular C function that save/restores all caller-save registers
• Inline handler gcc interrupt attribute to always callee-save every register (save as you go)
• EABI Task Group - improve interrupt latency by reducing the number of caller-save registers