RISC-V International
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Project Name | Base Architecture | Level of implementation | Notes |
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area-optimized core | RV32/64 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
high-performance core | RV32 | RTL simulation, FPGA Implementation, Synthesis | closed / commercial source https://www.seagate.com/innovation/risc-v/ |
microcontroller-class core | RV32IMAFC | RTL, fully synthesizable | Apache License, Version 2.0 https://github.com/T-head-Semi/opene906/blob/main/doc/opene906_datasheet.pdf |
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