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Status at a glance:

• Current  Definition-of-Done (wiki.riscv.org -> tech -> policies -> approved)   Status: kickoff  DoD status directory
• Next  update DoD checklist Plan tab, decide on any waivers needed?  Send to Chairs info below to transition from Kickoff to Plan  

To Reach Definition-of-Done Plan status: extension lifecycle and milestone definitions

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• [RVS-1017] Fast Interrupts (CLIC) - RISC-V Jira (riscv.org) 
  
  • CLIC ratification status is now tracked using Jira which includes links to google docs ratification plan and status checklist.

Charter

• Current Charter at https://github.com/riscv/groups/tree/main/Fast-Interrupts to be moved to  
• Calendar: https://githubcalendar.google.com/riscv-admin-docs (possibly renamed)calendar/u/0/embed?src=tech.meetings@riscv.org
• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
• Meetings Disclaimers Video

Specification

• Latest Draft Fast Interrupt Specification (v0.9-draft-2021070620240314)
• more CLIC memory mapped privilege regions clarification text.

What's next:

• 29 0 outstanding pre-ratification issues.
  • Freeze Checklist Completed

• Major items on Freeze Checklist: 

  • RISC-V SAIL 

  SAIL Implementation Completed 

  • RISC-V Tests 

  ACT tests created.  Missing SHV tests.

  • RISC-V Tests Input 

  riscv-software-src/riscv-config: RISC-V Configuration Validator (github.com) 

  Schema_isa.yaml - gives allowed configuration on risc-v and allowed values.  WARL fields give allowed ranges.  10k lines in file. 

  Examples/rivc32i_isa.yaml is compared against schema_isa.yaml to

  be addressed.  (previously 31).

  see if it is allowed. 

  When add new CSRs, add PR to add to schema_isa.yaml and then will be checked against example implementation. 

  Schemas/schema_platforml.yaml - memory mapped registers (like clicintctl, etc.) 

  Run python scripts that look at your implementation and see if it is valid.  e.g., if have d then have f- extenstion, etc. checks if WARL field is valid. 

  Write anything, read legal.  mapping from what is illegal to what is legal.  mapping is arbitrary.  so prefer (easiest) if implementers implement when write something illegal, don’t write.  that works easiest for describing in this file. 

Encoding/OpCode consistency review

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• No new instructions are added.  Needs to be aware CSR names?  Need to choose arch string like ziclic. Given that the key CSRs are in M-mode, it should probably be named something like "Smclic"

LLVM

• No new instructions are added.  Needs to be aware of CSR names? 

...

Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.

SAIL

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• which github?  https://github.com/rems-projectriscv/sail-riscv or https://github.com/riscv/riscv-sailAllen is working on this with the SAIL team from Cambridge.  ultimately it will be in the RISC-V repo as soon as we have maintainersthe official location

Spike

• TBD

riscvOVPSimPlus

• Imperas Commercial Simulator
• Freeware version

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Software

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• Regular C function that save/restores all caller-save registers
• Inline handler gcc interrupt attribute to always callee-save every register (save as you go)EABI Task Group - improve interrupt latency by reducing the number of caller-save registers
• psABI Task Group - https://github.com/riscv-non-isa/riscv-elf-psabi-doc
  • https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/eabi/eabi.adoc