RISC-V International
Page History
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- Draft Scalar Crypto Specification (v0.8.1)
- Stable
- What's next:
- Needs translation into ASCIIDOC
- Incorporate results of OpCode consistency review, once available
Need to discuss removing gorci
Encoding/OpCode consistency review
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- Test plan for the scalar-crypto specific instructions is available.
- No actual tests suitable for use currently available. An old experimental set need removing from the riscv-crypto repository, as these no longer work with the latest toolchain or architectural test framework.
- What's next: Currently exploring two paths:
- Imperas have a complete set of tests, written to the existing test plan, for the scalar crypto instructions and the bitmanip instructions we borrow.
- Some work required to re-generate them in a form suitable for merging into the main architectural test suite.
- These tests will be contributed upstream to the riscv-arch-test repository imminently, with many thanks to Imperas.
- They form a base we can use to develop prototype implementations / Spike / SAIL / QEMU very easily and quicklyNo exact estimate for how much work this is in days/weeks.
- IIT Madras are also looking at writing the scalar crypto tests for integration into the official architectural tests repo as well.
- No estimate for how long that would take yet.
- Meeting on Wednesday 24th Feb'21 to discuss this.
- Likely path is that they re-implement the tests as part of the blessed coverage and test generation tooling.
- We then switch over to using the IIT tests when they are finished, since they will be easier to maintain/extend going forward than the Imperas tests
- Ask Imperas to contribute their complete scalar-crypto + bitmanip subset tests.
- IIT Madras can then write the coverage plan for the architectural test framework.
- Any future changes to the contributed tests would need to be carefully managed, as they were not generated with the RISC-V test generator tool.
- Imperas have a complete set of tests, written to the existing test plan, for the scalar crypto instructions and the bitmanip instructions we borrow.
Compilers / Toolchains
GCC and Assembler
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| Project Name | Base Architecture | Level of implementation | Notes |
|---|---|---|---|
| scarv-cpu | RV32 | Behavioural RTL simulation . Running on FPGA. Post yosys synthesis results./ Yosys Synthesis / FPGA | Completely Public/Open Source. Useful as a public baseline. Commercial implementations should aim to be better than this! |
| PQShield security core | RV32 | (assumed) Behavioural RTL simulation. Running on FPGA. | Closed / commercial source. Most complete implementation of the entropy source. |
| Romain Dolbeau / VexRISC-V | RV32 | Running on FPGA. | Uses VexRiscv core as a base. Completely independent implementation from scratch, outside the Crypto TG. |
| croyde-riscv | RV64 | Behavioural RTL simulation / Yosys Synthesis / FPGA | 3-stage micro-controller. Implements rv64imck, machine + user mode. In development. Free/open source baseline for commercial implementations to do better than. |
- We still need a more RV64 implementation.I (Ben) am working on adding support to a toy core of mine, but I don't have much time to dedicate to this.implementations.
- Barry Spinney has offered to do advanced node synthesis runs for open source implementations.
- I (Ben) intend to take him up on this when I get time. No idea when that will be.
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