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Table of Contents

Overview

The RISC-V specification process is governed by the Ratification Policy and more concisely articulated in the Specification Lifecycle and Milestone Definitions presentation.  To help Task Group Chairs, Vice-chairs, and specification authors navigate this process, the RISC-V Lifecycle Guide has a whole section on "Specification Lifecycle" with an introductory section describing the process and subsections for each milestone that include step-by-step descriptions of the process.

This page serves as the starting point for understanding the status of specifications currently being developed by RISC-V.  This status is best represented as progress toward the key Specification Milestones (Plan, Freeze, and Ratification-ready) which are obtained sequentially.  Specific status for the relevant status columns is detailed in the Status Key section below.  The chairs and vice-chairs of Task Groups, specification authors, and Horizontal and ISA Committee chairs and vice-chairs jointly own ensuring their specifications are listed below and reflect accurate status.

In-process specifications are grouped below into two tables based on whether they impact the RISC-V ISA (In-process ISA Specifications) or not (In-process Non-ISA Specifications).  Items should have links to their respective specification repo (), Ratification Plan() if not a Fast-track item, and an Acceptance Criteria Status checklist (). 

Status of active votes by TSC and Committee Chairs can be found on the RISC-V Vote Status wiki page.

Completed specifications are tracked at the bottom of the page.

This dashboard does NOT intend to showed details status (that's available in the status checklist for the specification, ), but rather the general status in the journey to ratification. 

NOTE: This page is managed by the RISC-V staff with assistance from each specification owner. To get updates to this page or for questions, contact help@riscv.org.

In-process ISA Specification Status

Ratification Package 

: Project repo
: Plan doc
: Status chklist

extensions included


Task group approved by TSC dateSpecification State****Fast TrackPriv / UnprivCommittee (Owner)Task GroupPlan Milestone Target DateFreeze Milestone Target DateRatification Milestone Target DatePlan
Milestone Next Step*
Freeze
Milestone Next Step**
Ratification
Milestone Next Step***
Last UpdatedNotesIn RVA2023 profile as mandatory or supported optional

Advanced Interrupt Architecture (AIA)

  

Smaia, Ssaia

 

Public Review StartedNPPriv IC
(John Hauser, Anup Patel)
AIA
Q4'22

Q1'23

complete

complete

public review complete

  • Blanket waivers
  • Public review ends Dec. 24
y

Cache and Memory Controller QoS Register Interface (CMQRI)
  

Ssqosid

 

Plan CompleteNP

SOC Infrastructure HC (Eric Shiu, Ambika Krishnamoorthy)

CMQRI
Q2'23Q3'23completeacceptance criteria complete

 



Zca, Zcb, Zcd, Zcf, Zcmp, Zcmt2021FrozenNU

Unpriv IC

(Tariq Kurd)
Code Size Reduction
Q1'23Q1'23grandfathered

complete

public review complete

SAIL/ACT Waivers

ABI issues resolved

n
Zicond

 

NewYU

Unpriv IC
(Ved)

N/A
Q1'23





Debug

  


2020New

N

PPriv IC
(Tim Newsom)
Debug TG
Q2'23Q3'23review by chairs

acceptance criteria complete

start


n
Smclic2020Plan CompleteNPPriv IC
(Dan Smathers)
Fast Interrupts
Q1'23
N/A

spec development - stable

start?
n
Svadu

 

Plan  CompleteYPPriv IC
(Ved)
N/A
Q1'23Q1'23N/A

acceptance criteria complete


start



Zicntr, Zihpm

 

Public Review CompleteYUUnpriv IC
(Earl Killian)
N/A
Q4'22
N/A

complete

public review complete 

Review ends Dec. 23y
"May Be Ops" (for CFI, etc.) Zimop

 

StableYUUnpriv IC
(Andrew Waterman)
N/A
Q1'23
N/A

AR approval

start

08/22. need github specn
Zihintntl

 

Plan  CompleteYPPriv IC
(Andrew Waterman)
N/A
Q1'23
N/Aacceptance criteria completestart

Update needed.y
Zbpbo, Zpn, Zpsfoperand, P

2020

NewNUUnpriv IC
(Kevin Chen)
Packed SIMD
?
start

start


start


n
Zjid2020StableNPPriv IC
(Martin Maas)
I/D Consistency
Q1'23
N/A - GrandfatheredAR approvalstart

Spec in slide form, needs to be translated into write-up.?
Zjpm2020StableNPPriv IC
(Martin Maas)
Pointer Masking
Q1'23
N/A - GrandfatheredAR approvalstart

Waivers requested for SAIL and ACT.?

Profiles

  

Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa, Ssstateen, Ssptead, Sstvala, Sstvecd, Sstvecv, Ssu64xl, Svbare, Za128rs, Za64rs, Ziccamoa, Ziccif, Zicclsm, Ziccrse, Zic64b

 

Public Review StartedNUTSC
(Krste/Greg)
Profiles TG
Q4'22


complete

complete

 

public review complete

Public review ends 12/9.

y
RV32E/RV64E

 

Public Review CompleteYUUnpriv IC
(krste)
N/A
Q3'22Q4'22N/AcompleteTSC approval


n
Smrnmi

 

Plan  CompleteYPPriv IC
(Krste/Greg)
N/A
Q1'23
N/Aacceptance criteria completestart


n
Misc. basic Scalar FPZfa

 

Plan  CompleteYUUnpriv IC
(Andrew Waterman)
N/A
Q4'22Q1'23N/Aacceptance criteria completestart


y

Shadow Stacks and Landing Pads

Zisslpcfi

 

Plan  CompleteN U + P

Unpriv IC + Priv IC

(George, Ved)

SS-LP-CFI Q4'22Q3'23Q3'23Completestartstart


n
Sspmp

 

NewNPSecurity HC
(Dong Du)
S-Mode Physical Memory ProtectionQ4'22TBD
N/AN/AN/A


n

Total Store Ordering

Ztso

 

TSC ApprovedYUUnpriv IC
(Earl Killian)
N/A
Q3'22Q4'22N/A

complete

BOD approval


?

Vector Crypto

  

Zvkb, Zvkg, Zvknha, Zvknhb, Zvkns,  Zvksed, Zvksh

 

StableNU

Unpriv IC
(Ken Dockser)

Cryptographic Extensions
Q4'22Q1'23CompleteAR Approvalstart

SAIL & ACT Waivery

Vector Crypto - all-rounds AES

Zvknf

 

StableNU

Unpriv IC
(Ken Dockser)

Cryptographic Extensions
TBD
CompleteAR Approvalstart

SAIL & ACT Waivern

Vector IEEE FP16 Min Support, Arithmetic

Zvfh, Zvfhmin

 

StableYUUnpriv IC
(Krste)
N/A
Q4'22
N/A

freeze

start

Blanket waivery

In-process Non-ISA Specification Status

Ratification Package

: Project repo
: Plan doc
: Status chklist

Task group approved by TSC dateSpecification State****Committee (Owner)Task GroupPlan Milestone Target DateFreeze Milestone Target DateRatification Milestone Target DatePlan
Milestone next step*
Freeze
Milestone next step**

Ratification
Milestone next step

***

Last UpdatedNotes

Application Processor-Trusted Execution Environment (AP-TEE)

  

 

NewSecurity HC
(Ravi Sahita, Guerney Hunt)
AP-TEEQ1'23Q2'23Q2'23spec review stage


Architectural Test Requirements

  

2020New

ISA  Infrastructure HC
(Allen Baum)

Architecture Test SIG??


review by chairs



IOMMU

  

 

Plan  CompleteSOC Infrastructure HC
(Ved Shanbhogue, Perrine Peresse)
IOMMU
Q1'23
completeAR approval


IOPMP

 

New

Security HC
(Paul Ku)

IOPMP
Q3'23
review by chairs


Nexus Trace (control)

  

2020

NewSOC Infrastructure HC
(Robert Chylla)
Nexus Trace


review by chairs


PLIC

  

2020Public Review CompletePrivileged Software HC
(Abner Chang)


Q3'22Q4'22complete

complete

TSC approval


No waivers

RAS terms and definitions
 

 

NewSOC Infrastructure HC
(Dimitris Gizopoulos, Cameron McNairy)
RAS Terms and Defintions


build plan


Security Model

  

 

NewSecurity HC
(Xueyang Terry Wang, Suresh Sugumar)
Security Model


plan review by chairs


Unified Discovery (Config)

  

 

NewPrivileged Software HC
(Irma Flores-Mendoza
Unified Discovery
Q3'22
plan review by chairs

 


Watchdog Timer

  

 

New

Privileged Software HC
(Greg Favor, Anup Patel)





plan review by chairs



OS-A SEE

 

NewPrivileged Software HC
()









Platform Runtime Services

 

New

Privileged Software HC
()









RVV C Intrinsics

 

New

Applications & Tools HC
()










Status Key

The following steps and associated next sequential steps for the milestones listed in the tables above may be parallelized at times, but are most simply thought of as a sequential set.  All previous steps are done. They are as follows:

* Plan Milestone next Steps:

  1. build plan
  2. review by chairs
  3. complete (nothing else to do)

** Freeze Milestone next step:

  1. start
  2. spec development - stable
  3. AR approval (ISA/SW AR)
  4. acceptance criteria complete (including waivers, ar approval)
  5. committee chair approval
  6. freeze
  7. complete (nothing else to do)

*** Ratification Milestone next step (don't start until freeze is complete):

  1. start
  2. send out for public review
  3. public review complete
  4. acceptance criteria complete 
  5. committee chair approval
  6. TSC approval
  7. BOD approval
  8. ratified
  9. complete (nothing else to do)

**** Specification State values:

  1. New
  2. Plan Complete
  3. Stable
  4. Frozen
  5. Public Review Started
  6. Public Review Complete
  7. TSC Approved
  8. Ratified


Previously Ratified Specifications

2022

ISA Specifications

Ratification Package (Extension names)

: Project repo
: Plan doc
: Status chklist

Extension(s)Fast TrackPriv / UnprivCommittee (Owner)Task GroupPlan Milestone Target DateFreeze Milestone Target DateRatification Milestone Target DatePlan
Milestone Status*
Freeze
Milestone Status**
Ratification
Milestone Status***
Last UpdatedNotesIn RVA2023 profile as mandatory or supported optional
ZmmulYUUnpriv HC
(Allen Baum)


Q1'22Q2'22N/AFreeze Complete

 Ratification Complete


Unified Discovery Waiver
ZawrsYU

Unpriv HC
(Ved Shanbhogue)

N/A
Q2'22Q3'22N/A

complete

complete

11/7/22


y


Non-ISA Specifications

Specification

: Project repo
: Plan doc
: Status chklist

Committee
(Owner)
Task GroupPlan Milestone Target DateFreeze Milestone Target DateRatification Milestone Target DatePlan
Milestone Status*
Freeze
Milestone Status**
Ratification
Milestone Status***
Last UpdatedNotes

Efficient Trace (E-Trace)

  

SOC Infrastructure HC
(Gajinder Panesar)




Q2'22Plan CompleteFreeze Complete

Ratification Complete


  • No waivers
  • Needs copyright update

psABI

  

Privileged Software HC
(Kito Cheng, Jessica Clarke)

psABI
Q2'22Q3'22complete

complete

complete

11/7/22

No waivers

Supervisor Binary Interface (SBI)

  

Privileged Software HC
(Atish Patra)




Q2'22Plan CompleteFreeze Complete

Ratification Complete


No waivers

UEFI Protocol 

  

Privileged Software HC
(Sunil VL)



Q2'22Plan CompleteFreeze Complete

Ratification Complete


No waivers

2021

Ratification PackageFast TrackPriv UnprivExtension NamesOwnerArch ReviewStatus ChecklistPublic Review
Vector

N

UV, Zve32x, Zve32f, Zve64x, Zve64f, Zve64dKrsteCompleteCompleteY
Bit-ManipulationNUZba, Zbb, Zbc, ZbsKen / KrsteCompleteCompleteY
FP in INT regsNUZfinxTariqCompleteCompleteY
Half Width FPYU

Zfh, Zfhmin

AndrewCompleteCompleteY
ePMPNPSmepmpNickCompleteCompleteY
Crypto ScalarNUZbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, ZkrBenCompleteCompleteY
Priv 1.12NP

Sm1-12, Ss1-12, Sv57

GregCompleteCompleteY
CMO baseNPZicbom, Zicbop, ZicbozDavidKCompleteCompleteY
hypervisorNPHJohnHCompleteCompleteY
state enableYPSmstateenJohnHCompleteCompleteY

time cmp

YPSstcGregCompleteCompleteY
Count overflow & FilteringYPSscofmpfGregCompleteCompleteY
Fast TLB invalidationNPSvinval

Dan

CompleteCompleteY
NAPOT pagesNPSvnapotDanCompleteCompleteY
Page-based memory typesNPSvpbmtDanCompleteCompleteY
Pause HintYUZihintpauseGregCompleteCompleteY
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