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Specification
- Latest Draft Fast Interrupt Specification (v0.9-draft-20210422)
- updated adoc format to align with risc-v template, added revision history
- What's next:
- 35 outstanding issues to be addressed.
Encoding/OpCode consistency review
- Need to propose new CLIC CSR Registers and addresses to be proposed
- What's next: when outstanding issues are reduced, start planning for review
Architecture Tests
- Test plan for the fast-interrupt is available.
- YAML config needs to be created. See examples here.
Compilers / Toolchains
GCC and Binutils
- N/A? No new instructions are added. Needs to be aware CSR names? Need to choose arch string like ziclic
LLVM
- N/A? No new instructions are added. Needs to be aware of CSR names?
Simulators
Though all listed under "simulators", these are actually a collection of formal model / virtual machine / architectural simulators / DV simulators etc.
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Spike
riscvOVPSimPlus
- Imperas Commercial Simulator
- Freeware versionSupport for:
QEMU
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